This invention relates to a memory system using a charge coupled device, and in particular a memory system having a means for increasing a memory capacity.
A charge-coupled device (hereinafter referred to as "CCD") is adapted in a digital memory system. The reason is that CCD permits high density storage and it also allows a low cost memory system. An increased storage density of CCD will result in a memory system with increased capacity. One method for attaining increased capacity is to make the geometrical dimension of the memory cell or potential well of CCD small. However, reduction of the geometrical dimension of the memory cell provides a limitation from the standpoint of the manufacturing accuracy of CCD per se. Another method is to inject a multivalued signal with at least three information carrying voltage levels, in the form of electric charge, into CCD. A currently available CCD uses a binary (two-valued) signal having two voltage levels, i.e., "0" and "1". That is, only two information "0" and "1" are available in this case. However, difficulty arises as to how, for example, a three-valued signal with voltage levels "0", "1" and "2" is injected into CCD and each of the three voltage levels of the three-valued signal is correctly detected from the output of CCD. For this reason, a means for detecting such a multivalued signal from the output of CCD has not been realized to date. This provides a bar to marked increase of the storage capacity of a CCD built in memory system. It is accordingly the object of this invention to provide a memory system using CCD having a means for injecting a multivalued signal with at least three voltage levels, in the form of electric charge into CCD and detecting it from the output of CCD.